任职要求
• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.
学历要求:
• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field